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San Jose, CA
Mythri Ramesh Objective - Actively seeking Fall 2014 internship Education The University of Texas at Dallas, School of Engineering and Computer Science Present (Exp 2015) Master of Science in Electrical Engineering (Digital Systems) M S Ramaiah Institute of Technology May 2012 Bachelor of Engineering in Medical Electronics Skills Tools CAD Tools, Cadence, Synopsys, Encounter, Primetime, MATLAB, TetraMax, CPLEX Simulators HSPICE, ModelSim, Xilinx Lab instruments Oscilloscopes, ADC, waveform/signal generators, Signal Analysers, Multimeters, analog circuit simulators Programming Languages C, C++, Perl, Python Hardware Description Language VHDL, Verilog Operating Systems Windows, OS X, Linux Academic Projects SRAM Design and Layout Summer 2013 Tools used : Cadence Virtuoso, Synopsys, Hspice- Performed Automatic Placement and Routing (APRIL) using Encounter and verified by HSpice simulation Advanced Digital Logic Fall 2013 Tools used: Xilinx, modelsim, Synopsys, Tetramax- Designed, synthesized and simulated asynchronous sequential circuits.- Used Primetime and NCX to analyze and characterize library- Developed layouts and schematics of required gates in IBM 130 nm process in Cadence Virtuoso.- Simulated circuit for measuring the worst case read-write times and clock frequency. 21b * 21b Multiplier DesignTools used : Cadence, Hspice, PrimeTime- Continuous, cuff-less, non-invasive BP monitoring- Designed and developed layout of Min Area 128 word SRAM using the IBM 130nm process. * Performed DRC (for design rule checking) and LVS (for verifying that layout matches the schematic netlist)- Designed the schematic form of multiplier using IBM 130nm Technology- Cache Hierarchy was fine tuned for three individual benchmarks with - Cache levels, Unified Caches, Size, Associativity, Block size, Block replacement policy as design parameters. Design a Differential Amplifier Spring 2014 Using TSMC 0.35 micron process, designed a Differential Amplifier with active current mirror load in Cadence. Calculated ICMR, performed DC and AIR CONDITIONER sweep. Blood Pressure Monitoring using EEG and PPG Fall 2012 Tools used: Mathworks, SPSS software- Performed Post Design Validation on design of combinations of logic gates, found stuck-at faults, test vectors and fault coverage using Synopsys and Tetramax tools. Fine-tuning Cache Hierarchy of an Alpha Microprocessor Spring 2014 Tool used: Simplescalar- Verifying our design with Hspice where input operands are positive and output must drive a 15fF load. * Using Siliconsmart ACE to characterize your cells and finding power and delay from PrimeTime. 16-bit ALU using IBM 130nm technology (VLSI Project) Fall 2013 Tools used: Xilinx, Synopsys Design Vision, Cadence, HSpice, Encounter, Prime Time- Designed a 16-bit ALU using Verilog and generated gate level (RTL) design using Synopsys- ECG and PPG collected from 66 volunteers. Used Regression model for calculating SBP using PTT, arm length and weight Courses Graduate VLSI Design, Advanced Digital Logic, Computer Architecture, Analog IC Analysis and Design, Anatomy and Human Physiology for Engineers, Introduction to Cellular Microscopy(Current Course - Advanced VLSI) Undergraduate Microcontrollers, Signal and Systems, Digital Signal Processing, Digital Image Processing, Medical Image Processing
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August 1 on BarefootStudent